3236 scott boulevard santa clara, california 95054 phone: (408) 986-5060 fax: (408) 986-5095 cmm0530-lc features o multi-mode operation as low as 3.0v o 42% linear power added efficiency o 55% analog power added efficiency o new low-cost, plastic lcc-8 package o 29 db gain o tested under digital modulation o phemt material technology applications o is-98/amps handsets o is-136/amps cellular handsets o 900 mhz ism band products o wireless local loop subscriber terminals description the cmm0530-lc is a highly efficient multi-mode power amplifier gaas mmic intended for use in portable tele- phone handsets and data communications products for wireless communications. it meets the handset requirements for cellular amps, and the cdma and tdma digital standards for the us cellular wireless communications. cmm0530-lc is a member of the new triniti dx pro ? amplifier family whose members are pin-compatible and all operate under 3.5v bias voltage. the cmm0530-lc is packaged in a low-cost, plastic, lcc-8 power package. it has low thermal impedance and low rf loss. the device requires minimum amount of external biasing and rf matching circuits. 824 to 928 mhz 3.0v, 30.5 dbm multi-mode plastic lcc-8 power amplifier advanced product information may 1999 (1 of 4) ground tab v g2 1 n/c 4 v g1 2 rf in 3 7 rf out/v d2 8 n/c 5 v d1 6 rf out / v d2 ground tab functional block diagram recommended operating conditions parameter typ units parameter typ units drain voltage (+v d ) 3.0 to 4.2 volts operating temperature (pc board) -30 to +80 c absolute maximum ratings parameter rating parameter rating parameter rating drain voltage (+v d ) +5.5 v* power dissipation 5 w operating temperature -40c to +90c drain current (i d ) 1.8 a thermal resistance 20c/w channel temperature 150c rf input power +10 dbm* storage temperature -65c to +150c soldering temperature 260c for 5 sec. dc gate voltage (-v g ) -3.0 v* * max (+v d ) and (-v g ) under linear operation. max potential difference across the device at 1 db gain compression point (2v d + |-v g |) not to exceed the minimum breakdown voltage (v br ) of +12v. application information the cmm0530-lc is a two-stage amplifier that requires both positive and negative power supplies for proper operation. it is essential that the negative supply be applied first during turn-on and last during turn-off. otherwise, the device may be damaged. the cmm0530-lc can be operated over a wide range of positive and negative voltages to obtain various power, linearity and efficiency performance. however, it is important to keep the maximum dc power and the bias voltages within the speci- fied absolute maximum rating to prevent over stressing the device either electrically or thermally. design considerations biasing negative gate voltages are necessary to set the bias currents of the two fet stages in the cmm0530-lc. the first stage gate bias voltage is applied to vg1 (pin 2). the second stage gate bias voltage is applied to vg2 (pin 1). it is desirable to use one or more dacs (digital to analog converters) along with appropriate resistor divider networks, when necessary, in order to adjust the quiescent currents to within 10 ma of the targeted values. as an example, for cdma applications the tar- get quiescent current of the second fet is 120 ma, while that of the first is 50 ma. the total quiescent is 170 ma. it is also recommend that the quiescent currents be set in the following sequence: the second stage fet is set first, followed by the first stage fet. the negative supply voltages control the quiescent currents through each fet and, therefore, control the output power, adjacent channel power ratio, and the currents at full output power. the positive supply voltages are applied to pins 5, 6 and 7. it is very important to provide adequate de-coupling between the rf and the dc signals in designing the dc bias circuit. inadequate by-pass capacitance around the dc supply lines and inductance can compromise the adjacent channel power ratio (acpr), or reduce power gain and/or create oscil- lations. the recommend dc by-pass capacitance and low-pass C continued on page 2 C
3236 scott boulevard, santa clara, california 95054 phone: (408) 986-5060 fax: (408) 986-5095 digital bias analog bias parameter condition min typ max min typ max units frequency range 824 928 824 928 mhz pout - tdma operation meets is-136 tdma mask +30.0 dbm pout - cdma operation meets is-98 cdma mask +28.5 dbm pout - analog operation amps (under dual mode operation) +31.5 dbm efficiency is-136 tdma @ +30 dbm 42 % is-95 cdma @ +28 dbm 37 % amps @ +31.5 dbm (under dual mode operation) 55 57 % harmonics 2nd @ pout = +31.5 dbm -30 dbc 3rd @ pout = +31.5 dbm -35 dbc adjacent channel power pout = +30 dbm tdma 30 khz -26 dbc alternate channel power pout = +30 dbm tdma 60 khz -45 dbc adjacent channel power pout = +28 dbm cdma 898 khz -45 db c/30 khz alternate channel power pout = +28 dbm cdma 1980 khz -55 db c/30 khz noise power in receive band 30 khz bw -94 dbm gain @ pout = +28.5 dbm, +30 dbm 26 29 db @ pout = +31.5 dbm 24 27 db gain ripple 824-849 or 880-910 mhz 1.5 1.5 db gain variation over supply voltage 2 2 db/v gain variation over temperature 0.03 0.03 db/c power output control range vdd = 0 to 3.5 v 50 db quiescent current no rf, tdma mode 200 ma no rf, cdma mode 170 ma noise figure 3.5 3.5 db vswr input (in celeritek test fixture) 2.0:1 2.0:1 stability 8:1 vswr in band -80 -80 db c/30 khz 10:1 vswr out of band -80 -80 db c/30 khz electrical characteristics unless otherwise specified, the following specifications are guaranteed at room temperature with drain voltage (+v d ) = 3.5 v, in celeritek test fixture. cmm0530-lc advanced product information - may 1999 (2 of 4) in-line inductance are shown in the evaluation board on page 4. matching circuits output matching and input matching cir- cuits are required to achieve the rf specifications in this data sheet. the recommend matching circuits are identical to the matching circuits for the evaluation board shown on page 4. for output power matching, shunt capacitors along the trans- mission line connected to pins 6 and 7 as well as the bond wire inside the package from the output leads to the output fet are used to transform 50 impedance to the load line resistance of the output fet. the placements and the values of the capacitor are important in achieving the performance desired. matching circuits for frequencies other than the one shown can be achieved by changing the capacitor value and the placement position of the capacitor. the device can be designed to work from uhf to around 3 ghz. supply ramping to obtain power ramping, gate supply con- trol is recommended. drain supply voltage can also be used. modulation when biased as specified, the cmm0530-lc will achieve the required adjacent channel response for the digital system specified. celeritek tests each product under digital modulation to ensure correlation to customer applications. thermal 1. the copper pad on the backside of the cmm0530-lc must be soldered to the ground plane. 2. all 8 leads of the package must be soldered to the appropri- ate electrical connection. C continued from page 1 C typical performance gain & is-136 tdma output power vs frequency over voltage @ +25c frequency, mhz 824 849 27.5 29.5 29.5 31.5 gain, db 3.0 v 3.3 v 2.7 v power out, dbm 3.0 v 3.3 v 2.7 v
3236 scott boulevard santa clara, california 95054 phone: (408) 986-5060 fax: (408) 986-5095 cmm0530-lc advanced product information - may 1999 (3 of 4) is-98 cdma spectral mask (vdd = 3.5v) is-136 tdma spectral mask (vdd = 3.5v) channel power, dbc id & is-136 tdma channel power vs power output (3.5v, 836.5 mhz) id, ma -60 200 600 1000 8 31 -40 -20 adjacent channel power (worst case, fc 30 khz) alternate channel power (worst case, fc 60 khz) 13.75 19.5 25.25 power output, dbm (30 khz bw) wideband gain & return loss vs frequency @ 3.5v, +25c .3 40 30 20 10 0 gain, db gain input return loss output return loss .6 1.2 1.8 2.4 3.0 frequency, ghz -40 -30 -20 -10 0 return loss, db input output, dbm tdma power output and efficiency vs input power (3.5v, 836.5 mhz) 0 15 25 35 -24 +1 25 efficiency, % power output, dbm 5 -17 -11 -5 75 50 cdma power output and efficiency vs input power (3.5v, 836.5 mhz) input output, dbm 0 15 25 35 -9.0 -0.5 25 efficiency, % power output, dbm 5 -6.9 -4.9 -2.8 50 id & is-98 cdma channel power vs power output (3.5v, 836.5 mhz) power output, dbm (1.25 mhz bw) -75 100 400 700 -60 -45 channel power, dbc/30 khz adjacent channel power (worst case 0.898 mhz) adjacent channel power (worst case 1.98 mhz) id, ma 20 28.5 22.15 24.25 26.4 typical performance
n/c c4 100 pf c12 .01 f rf in cmm0530-lc rf out v gg c7 100 pf v dd 4 3 2 1 5 6 7 8 50 45 4@ 835 mhz 50 c6 10 pf l3 47 nh l2 47 nh l1 3.3 nh n/c 38 6 @ 835 mhz c9 .01 f c8 5600 pf c2 .01 f c1 10 f 65 8 835 mhz c3 100 pf c11 100 pf c10 5600 pf c13 100 f c5 2.2 pf r3 51 k 1.5 k 130 3236 scott boulevard, santa clara, california 95054 phone: (408) 986-5060 fax: (408) 986-5095 celeritek reserves the right to make changes without further notice to any products herein. celeritek makes no warranty, repres entation or guarantee regarding the suitability of its products for any particular purpose, nor does celeritek assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters can and do vary in different applications. all operating parameters, including typicals must be validated for each customer application by customers technical experts. celeritek doe s not convey any license under its patent rights nor the rights of others. celeritek products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the celeritek prod uct could create a situation where personal injury or death may occur. should buyer purchase or use celeritek products for any such unintended or unauthorized application, buyer shall indemnify and hold celeritek and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that celeritek was negligent regarding the design or manufacture of the part. celeritek is a registered trademark of celeritek, inc. celeritek, inc. is an e qual opportunity/affirmative action employer. ordering information the cmm0530-lc is available in a surface mount wide-body msop-8 power package and devices are available in tape and reel. part number for ordering package cmm0530-lc-00s0 lcc-8 cdma surface mount power package CMM0530-LC-00T0 lcc-8 tdma surface mount power package cmm0530-lc-00st lcc-8 cdma surface mount power package in tape and reel cmm0530-lc-00tt lcc-8 tdma surface mount power package in tape and reel pb-cmm0530-lc-00s0 evaluation board with sma connectors for cmm0530-lc-00s0 pb-CMM0530-LC-00T0 evaluation board with sma connectors for CMM0530-LC-00T0 physical dimensions cmm0530-lc advanced product information - may 1999 (4 of 4) evaluation board schematic board substrate: er = 4.60 thickness = 0.031 in. recommended matching topology note: this schematic represents the topology of the matching circuit recommended by celeritek.
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